M.TECH, M.E / B.TECH, BE Final Year Projects BASED ON VERILOG, VHDL, SYSTEM VERILOG, XILINX VIVADO, FPGA

VLSI Technology is a company that designed and manufactured custom and semi-custom integrated circuits (ICs). Nowadays VLSI technology is widely used in various branches of Engineering like Electronics & Communications, Digital Signal Processing, Computers, Commercial Electronics, Automobiles, Robotics and many more. VLSI full form Very-large-scale integration (VLSI) design is the process of creating an integrated circuit (IC) by combining thousands of transistors into a single chip.

SD Pro Solutions Provide VLSI projects are implemented in either in Verilog HDL or VHDL coding using Modelsim& Xilinx Software. Then the bit code is generated from this which can be dumped on FPGA Boards. M. Tech VLSI projects can be implemented using IEEE VLSI Papers. Its include the kit implementation which can be done on Virtex Board & Spartan Family Boards Like Spartan 3, Spartan 3a, Spartan 3e and Spartan 6 based on the chosen.

We also offer IEEE & Non IEEE based VLSI projects for final year students from ECE and M. Tech VLSI & Embedded Systems, Digital Electronics. We have a large Number of IEEE Transaction VLSI projects, Students can select in the domain which they are interested in. will offer Major & Mini Projects in VLSI Domain.

We are giving a Idea & knowledge on industrial tool specifications such as cadence orcad, Xilinx Vivado, Tanner EDA, AVR studio, MATLAB, H-spice, P-spice, Modelsim, Network simulator2, Proteaus and many more to follow.

We are one of the finest companies in Bangalore to suggest research-based projects for M.Tech VLSI which is helpful in advancing their career.

IEEE VLSI Projects 2019-20

  • 2019 – 2020
  • 2018 – 2019
S.No TITLE DOMAIN YEAR BASE PAPER
1 A Two-Speed, Radix-4, Serial–Parallel Multiplier Area Efficient 2019 Download
2 Feed forward-Cut set-Free Pipelined Multiply–Accumulate
Unit for the Machine Learning Accelerator
Area Efficient 2019 Download
3 New Majority Gate Based Parallel BCD Adder Designs for
Quantum-dot Cellular Automata
Area Efficient 2019 Download
4 Efficient Design for Fixed-Width Adder-Tree Area Efficient 2019 Download
5 Area–Delay–Energy Efficient VLSI Architecture for Scalable
In-Place Computation of FFT on Real Data
Area Delay Power Efficient 2019 Download
6 Fast HUB Floating-point Adder for FPGA High Speed 2019 Download
7 Tunable Floating-Point Adder Low Power 2019 Download
8 Energy-Quality Scalable Adders Based on Non zeroing Bit
Truncation
Low Power 2019 Download
9 Dual-Channel Multiplier for Piecewise-Polynomial Function
Evaluation for Low-Power 3-D Graphics
Low Power 2019 Download
10 A High Performance, Low Energy, Compact Masked 128-Bit AES
in 22nm CMOS Technology
Low Power 2019 Download
11 Concurrent Error Detectable Carry Select Adder with Easy
Testability
Error Correction 2019 Download
12 Design and Analysis of Approximate Redundant Binary
Multipliers
Error Correction 2019 Download
13 A Further Optimized Mix Column Architecture Design for the
Advanced Encryption Standard
Security 2019 Download
14 Architecture Optimization and Performance Comparison of
Nonce-Misuse-Resistant Authenticated Encryption Algorithms
Security 2019 Download
15 Modified Dual-CLCG Method and Its VLSI Architecture for
Pseudorandom Bit Generation
Testing 2019 Download
16 Hardware-Efficient Post-processing Architectures for True
Random Number Generators
Testing 2019 Download
17 Robust Design-for-Security Architecture for Enabling Trust
in IC Manufacturing and Test
Testing 2018 Download
18 RTHS: A Low-Cost High-Performance Real-Time Hardware
Sorter, Using a Multidimensional Sorting Algorithm
IP + VLSI Application 2019 Download
19 Approximate DCT Design for Video Encoding Based on Novel
Truncation Scheme
IP + VLSI Application 2019 Download
20 High-Throughput Multi filter Interpolation Architecture for
AV1 Motion Compensation
IP + VLSI Application 2019 Download
21 Design Methodology to Explore Hybrid Approximate Adders for
Energy-Efficient Image and Video Processing Accelerators
IP + VLSI Application 2019 Download
22 A Majority-Based Imprecise Multiplier for Ultra-Efficient
Approximate Image Multiplication
IP + VLSI Application 2019 Download
23 Multiplier-less Stream Processor for 2D Filtering in Visual
Search Applications
IP + VLSI Application 2018 Download
24 Low-Cost Sorting Network Circuits Using Unary Processing IP + VLSI Application 2018 Download
CODE TITLE DOMAIN YEAR
SDVL-01 Multiplier-less Stream Processor for 2D Filtering in Visual Search Applications Area Efficient 2018
SDVL-02 Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification Area Efficient 2018
SDVL-03 Adaptive Precision Cellular Nonlinear Network Area Efficient 2018
SDVL-04 Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers Area Efficient 2018
SDVL-05 Decimal Full Adders Specially Designed for Quantum-Dot Cellular Automata Area Efficient 2018
SDVL-06 Improved Algorithms and Implementations for Integer to τNAF Conversion for Koblitz Curves High Speed 2018
SDVL-07 Tap Delay-and-Accumulate Cost Aware Coefficient Synthesis Algorithm for the Design of Area-Power Efficient FIR Filters High Speed 2018
SDVL-08 A Simple Yet Efficient Accuracy-Configurable Adder Design Low Power 2018
SDVL-09 Low-Power Addition With Borrow-Save Adders Under Threshold Voltage Variability Low Power 2018
SDVL-10 Low-Cost Sorting Network Circuits Using Unary Processing Low Power 2018
SDVL-11 Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks Low Power Security 2018
SDVL-12 Secure and Lightweight Compressive Sensing using Stream Cipher Security 2016
SDVL-13 Toward Energy-Efficient Stochastic Circuits Using Parallel Sobol Sequences Error Correction 2018
SDVL-14 Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications Error Correction 2018
SDVL-15 Efficient Fault Tolerant Design for Parallel Matched Filters Error Correction 2018
SDVL-16 A Low Error Energy-Efficient Fixed-Width Booth Multiplier with Sign-Digit-Based Conditional Probability Estimation Error Correction 2018
SDVL-17 Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test Testing 2018
SDVL-18 Energy-Efficient Scheme for Multiple Scan-Chains BIST Using Weight-Based Segmentation Testing 2018
SDVL-19 A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits Area, Delay Power Efficient 2018
SDVL-20 RAP-CLA: A Reconfigurable Approximate Carry Look-Ahead Adder Area, Delay Power Efficient 2018
SDVL-21 Feed forward FFT Hardware Architectures Based on Rotator Allocation Error Correction 2017
SDVL-22 Low-Latency, Low-Area, and Scalable Systolic-Like Modular Multipliers for GF(2m) Based on Irreducible All-One Polynomials Area Efficient 2017
SDVL-23 Weighted Partitioning for Fast Multiplier less Multiple-Constant Convolution Circuit Area Efficient 2017
SDVL-24 FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over GF(2m) and Their Applications in Trinomial Multipliers Area Efficient 2017
SDVL-25 Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding Area Efficient 2016

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